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| tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 1/49 tentative toshiba mos digital integrated circuit silicon monolithic 8,388,608-words 4 banks 16-bits synchronous dynamic ram 16,777,216-words 4 banks 8-bits synchronous dynamic ram 33,554,432-words 4 banks 4-bits synchronous dynamic ram description 7& 60 $)7$)7/ lv d &026 v\qfkurqrxv g\qdplf udqgrp dffhvv phpru\ rujdql]hg dv zrugv edqnv elwv dqg 7& 60 $)7$)7/ lv rujdql]hg dv zrugv edqnv elwv dqg 7kh 7& 60 $)7$)7/ lv rujdql]hg dv zrugv edqnv elwv )xoo\ v\qfkurqrxv rshudwlrqv duh uhihuhqfhg wr wkh srvlwlyh hgjhv ri forfn lqsxw dqg fdq wudqvihu gdwd xs wr 0 zrugv shu vhfrqg 7khvh ghylfhv duh frqwuroohg e\ frppdqgv vhwwlqj (dfk edqn duh nhsw dfwlyh vr wkdw '5$0 fruh vhqvh dpsolilhuv fdq eh xvhg dv d fdfkh 7kh uhiuhvk ixqfwlrqv hlwkhu $xwr 5hiuhvk ru 6hoi 5hiuhvk duh hdv\ wr xvh %\ kdylqj d surjudppdeoh 0rgh 5hjlvwhu wkh v\vwhp fdq fkrrvh wkh prvw vxlwdeoh prghv zklfk zloo pd[lpl]h lwv shuirupdqfh 7khvh ghylfhv duh lghdo iru pdlq phpru\ lq dssolfdwlrqv vxfk dv zrunvwdwlrqv features tc59sm916/m908/m904 parameter -70 -75 -80 t ck clock cycle time (min) 7 ns 7.5 ns 8 ns t ras active to precharge command period (min) 40 ns 45 ns 48 ns t ac access time from clk (max) 5.4 ns 5.4 ns 6 ns t rc ref/active to ref/active command period (min) 56 ns 65 ns 68 ns i cc1 operation current (max) (single bank) tbd tbd tbd i cc4 burst operation current (max) tbd tbd tbd i cc6 self-refresh current (max) tbd tbd tbd ? 6lqjoh srzhu vxsso\ ri 9 9 ? 8s wr 0+] forfn iuhtxhqf\ ? 6\qfkurqrxv rshudwlrqv $oo vljqdov uhihuhqfhg wr wkh srvlwlyh hgjhv ri forfn ? $ufklwhfwxuh 3lsholqh ? 2ujdql]dwlrq 7& 60 $)7$)7/ zrugv edqnv elwv 7& 60 $)7$)7/ zrugv edqnv elwv 7& 60 $)7$)7/ zrugv edqnv elwv ? 3urjudppdeoh 0rgh uhjlvwhu ? $xwr 5hiuhvk dqg 6hoi 5hiuhvk ? %xuvw /hqjwk )xoo sdjh ? &$6 /dwhqf\ ? 6lqjoh :ulwh 0rgh ? %xuvw 6wrs )xqfwlrq ? %\wh 'dwd &rqwuroohg e\ /'40 8'40 7& 60 ? . 5hiuhvk f\fohv pv ? ,qwhuidfh /977/ ? 3dfndjh 7& 60 $)7$)7/ 7623,,3% 7& 60 $)7$)7/ 7623,,3% 7& 60 $)7$)7/ 7623,,3% ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage t o property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume nt shall be made at the customer?s own risk. 000707 eba2
tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 2/49 pin names pin assignment (top view) a0~a12 address input bs0, bs1 bank select dq0~dq3 (tc59sm904) dq0~dq7 (tc59sm908) dq0~dq15 (tc59sm916) data input/output cs chip select ras row address strobe cas column address strobe we write enable dqm (tc59sm908/m904) udqm/ldqm (tc59sm916) output disable/write mask clk clock input cke clock enable v cc power ( + 3.3 v) v ss ground v ccq power ( + 3.3 v) (for dq buffer) v ssq ground (for dq buffer) nc no connection tc59sm916aft/aftl tc59sm908aft/aftl tc59sm904aft/aftl v ss nc v ssq nc dq3 v ccq nc nc v ssq nc dq2 v ccq nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 1 045 1 144 1 243 1 342 1 441 1 540 1 639 1 738 1 837 1 936 2 035 2 134 2 233 2 332 2 431 2 530 2 629 2 728 v ss dq7 v ssq nc dq6 v ccq nc dq5 v ssq nc dq4 v ccq nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss v ss d q15 v ssq d q14 d q13 v ccq d q12 d q11 v ssq d q10 d q9 v ccq d q8 v ss n c u dqm c lk c ke a 12 a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss v cc dq0 v ccq dq1 dq2 v ssq dq3 dq4 v ccq dq5 dq6 v ssq dq7 v cc ldqm bs0 bs1 a10/ap a0 a1 a2 a3 v cc we cas ras cs v cc dq0 v ccq nc dq1 v ssq nc dq2 v ccq nc dq3 v ssq nc v cc nc bs0 bs1 a10/ap a0 a1 a2 a3 v cc we cas ras cs v cc nc v ccq nc dq0 v ssq nc nc v ccq nc dq1 v ssq nc v cc nc bs0 bs1 a10/ap a0 a1 a2 a3 v cc we cas ras cs ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000707 eba2 tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 3/49 block diagram note: the tc59sm904aft/aftl configuration is 8192 4096 4 of cell array with the dq pins numbered dq0~dq3. the tc59sm908aft/aftl configuration is 8192 2048 8 of cell array with the dq pins numbered dq0~dq7. the tc59sm916aft/aftl configuration is 8192 1024 16 of cell array with the dq pins numbered dq0~dq15. cke a10 cell array bank #0 column decoder sense amplifier row decoder dq0~dqn cell array bank #3 column decoder sense amplifier row decoder cell array bank #2 column decoder sense amplifier row decoder mode register clock buffer clk cas we a0~a9 a11, a12 bs0 bs1 dqm cs cell array bank #1 column decoder sense amplifier row decoder control signal generator ras command decoder address buffer refresh counter column counter data control circuit dq buffer tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 4/49 absolute maximum ratings symbol parameter rating units notes v in , v out input, output voltage ? 0.3~v cc + 0.3 v 1 v cc , v ccq power supply voltage ? 0.3~4.6 v 1 t opr operating temperature 0~70 c1 t stg storage temperature ? 55~150 c1 t solder soldering temperature (10s) 260 c1 p d power dissipation 1 w 1 i out short-circuit output current 50 ma 1 recommended dc operating conditions (ta = 0~70c) symbol parameter min typ. max units notes v cc power supply voltage 3 3.3 3.6 v 2 v ccq power supply voltage (for dq buffer) 3 3.3 3.6 v 2 v ih lvttl input high voltage 2 ? v cc + 0.3 v 2 v il lvttl input low voltage ? 0.3 ? 0.8 v 2 note: v ih (max) = v cc /v ccq + 1.2 v for pulse width 5ns v il (min) = v ss /v ssq ? 1.2 v for pulse width 5 ns v ccq must be less than or equal to v cc . capacitance (v cc = 3.3 v, f = 1 mhz, ta = 25c) symbol parameter min max unit input capacitance (a0~a12, bs0, bs1, cs , ras , cas , we , dqm * , cke) ? 4pf c i input capacitance (clk) ? 5pf c o input/output capacitance ? 6.5 pf note: these parameters are periodically sampled and not 100% tested. * ldqm, udqm (tc59sm916) tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 5/49 dc characteristics (v cc = 3.3 v 0.3 v, ta = 0 ~70 c) -70 -75 -80 parameter symbol min max min max min max units notes operating current t ck = min, t rc = min active precharge command cycling without burst operation 1 bank operation i cc1 ? tbd ? tbd ? tbd 3 cke = v ih i cc2 ? tbd ? tbd ? tbd 3 standby current t ck = min, cs = v ih , v ih/l = v ih (min) / v il (max), bank: inactive state cke = v il (power down mode) i cc2p ? 1 ? 1 ? 13 cke = v ih i cc2s ? tbd ? tbd ? tbd standby current clk = v il , cs = v ih , v ih/l = v ih (min) / v il (max), bank: inactive state cke = v il (power down mode) i cc2ps ? 1 ? 1 ? 1 cke = v ih i cc3 ? tbd ? tbd ? tbd no operating current t ck = min, cs = v ih (min), bank: active state (4 banks) cke = v il (power down mode) i cc3p ? 10 ? 10 ? 10 burst operating current t ck = min read/write command cycling i cc4 ? tbd ? tbd ? tbd 3, 4 auto refresh current t ck = min, t rc = min auto refresh command cycling i cc5 ? tbd ? tbd ? tbd 3 standard products (aft) ? tbd ? tbd ? tbd self refresh current self refresh mode cke = 0.2 v low power version (aftl) i cc6 ? tbd ? tbd ? tbd ma parameter symbol min max units notes input leakage current (0 v v in v cc , all other pins not under test = 0 v) i i (l) ? 55 a output leakage current (output disable, 0 v v out v ccq ) i o (l) ? 55 a lvttl output h level voltage (i out = ? 2 ma) v oh 2.4 ? v lvttl output l level voltage (i out = 2 ma) v ol ? 0.4 v tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 6/49 ac characteristics and operating conditions (v cc = 3.3 v 0.3 v, ta = 0 ~70 c) (notes: 5, 6, 7) -70 -75 -80 symbol parameter min max min max min max units notes t rc ref/active to ref/active command period 56 ? 65 ? 68 ? t ras active to precharge command period 40 100000 45 100000 48 100000 t rcd active to read/write command delay time 15 ? 20 ? 20 ? ns t ccd read/write(a) to read/write(b) command period 1 ? 1 ? 1 ? cycle t rp precharge to active command period 15 ? 20 ? 20 ? t rrd active(a) to active(b) command period 15 ? 15 ? 20 ? cl * = 2 7.5 ? 10 ? 10 ? t wr write-recovery time cl * = 37 ? 7.5 ? 8 ? cl * = 2 7.5 1000 10 1000 10 1000 t ck clk cycle time cl * = 3 7 1000 7.5 1000 8 1000 t ch clk high-level width 2.5 ? 2.5 ? 3 ? t cl clk low-level width 2.5 ? 2.5 ? 3 ? cl * = 2 ? 5.4 ? 6 ? 6 t ac access time from clk cl * = 3 ? 5.4 ? 5.4 ? 6 t oh output data hold time 3 ? 3 ? 3 ? t hz output data high-impedance time 3 7 3 7.5 3 8 t lz output data low-impedance time 0 ? 0 ? 0 ? t sb power-down mode entry time 0 7 0 7.5 0 8 t t transition time of clk (rise and fall) 0.5 10 0.5 10 0.5 10 t ds data-in set-up time 1.5 ? 1.5 ? 2 ? t dh data-in hold time 0.8 ? 0.8 ? 1 ? t as address set-up time 1.5 ? 1.5 ? 2 ? t ah address hold time 0.8 ? 0.8 ? 1 ? t cks cke set-up time 1.5 ? 1.5 ? 2 ? t ckh cke hold time 0.8 ? 0.8 ? 1 ? t cms command set-up time 1.5 ? 1.5 ? 2 ? t cmh command hold time 0.8 ? 0.8 ? 1 ? ns t ref refresh time ? 64 ? 64 ? 64 ms t rsc mode register set cycle time 14 ? 15 ? 16 ? ns * cl means cas latency. tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 7/49 127(6 &rqglwlrqv rxwvlgh wkh olplwv olvwhg xqghu $%62/87( 0$;,080 5$7,1*6 pd\ fdxvh shupdqhqw gdpdjh wr wkh ghylfh $oo yrowdjhv duh uhihuhqfhg wr 9 66 7khvh sdudphwhuv ghshqg rq wkh f\foh udwh dqg wkhvh ydoxhv duh phdvxuhg dw d f\foh udwh zlwk wkh plqlpxp ydoxhv ri w &. dqg w 5& ,qsxw vljqdov duh fkdqjhg rqh wlph gxulqj w &. 7khvh sdudphwhuv ghshqg rq wkh rxwsxw ordglqj 6shflilhg ydoxhv duh rewdlqhg zlwk wkh rxwsxw rshq 3rzhuxs vhtxhqfh lv ghvfulehg lq 1rwh $& 7(67 &21',7,216 output reference level 1.4 v, 1.4 v output load see diagram b below input signal levels 2.4 v, 0.4 v transition time (rise and fall) of input signals 2 ns input reference level 1.4 v w += ghilqhv wkh wlph dw zklfk wkh rxwsxwv dfklhyh wkh rshq flufxlw frqglwlrq dqg lv qrw uhihuhqfhg wr rxwsxw yrowdjh ohyhov ac test load (a) output 3.3 v 870 ? 5 0 pf 1.2 k ? ac test load (b) output 1.4 v 50 pf 50 ? z = 50 ? tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 8/49 7khvh sdudphwhuv dffrxqw iru wkh qxpehu ri forfn f\fohv dqg ghshqg rq wkh rshudwlqj iuhtxhqf\ ri wkh forfn dv iroorzv wkh qxpehu ri forfn f\fohv = vshflilhg ydoxh ri wlplqj forfn shulrg frxqw iudfwlrqv dv d zkroh q xpehu 3rzhuxs 6htxhqfh 3rzhuxs pxvw eh shuiruphg lq wkh iroorzlqj vhtxhqfh 3rzhu pxvw eh dssolhg wr 9 && dqg 9 &&4 vlpxowdqhrxvo\ zkloh doo lqsxw vljqdov duh khog lq wkh 123 vwdwh 7kh &/. vljqdov pxvw eh vwduwhg dw wkh vdph wlph $iwhu srzhuxs d sdxvh ri dw ohdvw v lv uhtxluhg ,w lv uhtxluhg wkdw '40 dqg &.( vljqdov pxvw eh khog +ljk 9 && ohyhov wr hqvxuh wkdw wkh '4 rxwsxw lv lq +ljklpshgdqfh vwdwh $oo edqnv pxvw eh suhfkdujhg 7kh 0rgh 5hjlvwhu 6hw frppdqg pxvw eh dvvhuwhg wr lqlwldol]h wkh 0rgh 5hjlvwhu $ plqlpxp ri hljkw $xwr 5hiuhvk gxpp\ f\fohv lv uhtxluhg wr vwdelol]h wkh lqwhuqdo flufxlwu\ ri wkh ghylfh 7kh 0rgh 5hjlvwhu 6hw frppdqg fdq eh lqyrnhg hlwkhu ehiruh ru diwhu wkh $xwr 5hiuhvk gxpp\ f\fohv $& /dwhqf\ &kdudfwhulvwlfv cke to clock disable (cke latency) 1 dqm to output in high-z (read dqm latency) 2 dqm to input data delay (write dqm latency) 0 write command to input data (write data latency) 0 cs to command input ( cs latency) 0 cl = 22 precharge to dq hi-z lead time cl = 33 cl = 21 precharge to last valid data out cl = 32 cl = 22 burst stop command to dq hi-z lead time cl = 33 cl = 21 burst stop command to last valid data out cl = 32 cycle cl = 2bl + t rp read with autoprecharge command to active/ref command cl = 3bl + t rp cl = 2bl + t rp write with autoprecharge command to active/ref command cl = 3bl + t rp cycle + ns tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 9/49 timing diagrams command input timing ras t ck t cl t ch t cms t cmh t cms t cmh t cms t cmh cs cas t cms t cmh we t cms t cmh a0~a12 bs0, bs1 t as t ah t ckh t cks t cks t ckh t cks t ckh cke clk v ih v il tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 10/49 read timing ras read cas latency cs cas we a0~a12 bs0, bs1 t ac dq clk t oh t hz t oh t ac burst length t lz output data valid output data valid read command tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 11/49 control timing of input data (tc59sm908/m904) control timing of output data (tc59sm908/m904) dq0~dq7 (dq0~dq3) * dqm clk t cmh t cms t cmh t cms t ac t oh t ac t lz t ac t oh t hz t oh output data valid output data valid (output enable) (clock mask) output data valid t ac t oh dq0~dq7 (dq0~dq3) * cke clk t ckh t cks t ckh t cks t oh t ac t oh t ac t oh output data valid output data valid t ac t ac t oh output data valid open * : tc59sm804 dq0~dq7 (dq0~dq3) * dqm clk t cmh t cms t cmh t cms t dh t ds input data valid input data valid input data valid input data valid cke clk t ckh t cks t ckh t cks t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid input data valid (word mask) (clock mask) dq0~dq7 (dq0~dq3) * t dh t ds t dh t ds t dh t ds tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 12/49 control timing of input data (tc59sm916) input data valid udqm ldqm clk t cmh t cms t cmh t cms t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid input data valid t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid (word mask) dq0~dq7 dq8~dq15 t cmh t cms t cmh t cms cke clk t ckh t cks t ckh t cks t dh t ds input data valid t dh t ds t dh t ds input data valid input data valid (clock mask) dq8~dq15 t dh t ds input data valid t dh t ds input data valid dq0~dq7 t dh t ds t dh t ds input data valid input data valid t dh t ds input data valid tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 13/49 control timing of output data (tc59sm916) cke clk t ckh t cks t ckh t cks t oh t ac t oh t ac output data valid output data valid (clock mask) dq0~dq7 output data valid t oh t oh t ac t ac t oh t oh output data valid output data valid dq8~dq15 output data valid t oh t oh t ac t ac t ac t ac udqm ldqm clk t cmh t cms t cmh t cms t lz t ac t oh t ac t oh t hz output data valid output data valid (output enable) dq0~dq7 t cmh t cms t cmh t cms output data valid t oh t ac t oh t ac t oh t ac output data valid dq8~dq15 output data valid t oh t ac t oh t ac output data valid t oh t hz open t lz t ac open tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 14/49 mode register set cycle a0 a1 a2 burst length a3 addressing mode a4 a5 a6 cas latency a7 0 (test mode) a8 0 reserved a9 write mode a10 0 a11 0 a12 0 bs0 0 bs1 0 reserved burst length a2 a1 a0 sequential interleaved 000 1 1 001 2 2 010 4 4 011 8 8 100 101 110 reserved 1 1 1 full page reserved a3 addressing mode 0 sequential 1 interleaved a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved a9 single write mode 0 burst read and burst write 1 burst read and single write ras t rsc t cms t cmh cs cas we a0~a12 bs0, bs1 clk t cms t cmh t cms t cmh t cms t cmh t as t ah set register data next command tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 15/49 operating timing example figure 1. interleaved bank read (burst length = 4, latency = 3) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras ras cs cas t rc t rc t rc we bs0 raa rbb rac rbd rae a10 raa caw cbx rac cay rbd cbz rae a0~a9, a11, a12 dqm cke aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dq t rrd t rrd t rrd t rrd active read active read active precharge precharge read read precharge active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac rbb cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 16/49 figure 2. interleaved bank read (burst length = 4, latency = 3, auto precharge) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras ras cs cas t rc t rc t rc we bs0 raa rac rbd rae a10 raa cbx rac cay a0~a9, a11, a12 dqm cke aw0 bx0 cy0 dq t rrd t rrd t rrd t rrd active read active read active read active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac rbb caw rbb rbd cbz rae aw1 aw2 aw3 bx1 bx2 bx3 cy1 cy2 cy3 dz0 ap * read ap * ap * * : ap shows internal precharge start timing. cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 17/49 figure 3. interleaved bank read (burst length = 8, latency = 3) a0~a9, a11, a12 clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras ras cs cas t rc t rc t rc we bs0 raa rbb rac a10 raa cby dqm cke ax0 by0 by4 dq t rrd t rrd active read read active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t ras t rp t rp t ras t rcd t rcd t rcd t ac t ac t ac cax rac caz ax1 ax2 ax3 by5 by6 by7 precharge rbb ax4 ax5 ax6 by1 cz0 precharge read precharge cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 18/49 figure 4. interleaved bank read (burst length = 8, latency = 3, auto precharge) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t rc t ras ras cas t rc we bs0 raa rbb rac a10 raa cby a0~a9, a11, a12 dqm cke ax0 by0 dq t rrd t rrd active read active active bank#0 bank#2 bank#3 bank#1 idle bs1 t ras t rp t rp t ras t rcd t rcd t rcd t ac t ac t ac cax rac caz ax1 ax2 ax3 by4 by5 by6 * : ap shows the internal precharge start timing. rbb ax4 ax5 ax6 by1 read ax7 cz0 ap * read ap * cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 19/49 figure 5. interleaved bank write (burst length = 8) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t ras ras cas t rc we bs0 raa rbb rac a10 raa cby a0~a9, a11, a12 dqm cke ax0 by0 dq t rrd t rrd active write active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t rp t ras cax rac caz ax1 by4 by5 by6 rbb ax4 ax5 ax6 by1 ax7 precharge t rcd t rcd t rcd by2 by3 by7 cz0 cz1 cz2 write write precharge tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 20/49 figure 6. interleaved bank write (burst length = 8, auto precharge) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t ras ras cas t rc we bs0 raa rbb rab a10 raa cby a0~a9, a11, a12 dqm cke ax0 by0 dq t rrd t rrd active write active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t rp t ras t rcd t rcd t rcd cax rac caz ax1 by4 by5 by6 rbb ax4 ax5 ax6 by1 ax7 by2 by3 by7 cz0 cz1 cz2 t ras ap * write ap * write * : ap shows the internal precharge start timing. tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 21/49 figure 7. page mode read (burst length = 4, latency = 3) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ras cs cas t ras we bs0 raa a10 raa cay a0~a9, a11, a12 dqm cke bx1 dq t rrd active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rcd t rcd cal cbz bz0 rbb al0 al1 ay0 ay1 ay2 ap * * : ap shows the internal precharge start timing. t ccd t ccd t ccd t ras t rp t rp rbb cbx cam al2 al3 bx0 am0 am1 am2 bz1 bz2 bz3 t ac t ac t ac t ac t ac read read read read read precharge cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 22/49 figure 8. page mode read/write (burst length = 8, latency = 3) a0~a9, a11, a12 ras cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 t ras cs t rp cke bs1 dqm bs0 raa a10 t rcd raa cax cay dq active read precharge bank#0 bank#2 bank#3 bank#1 idle ax0 ax1 ax2 ax3 ax4 we ax5 ay0 ay1 ay2 ay3 ay4 qqqqqq ddddd t wr t ac note): see figure 17, 20 write 22 cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 23/49 figure 9. auto precharge read (burst length = 4, latency = 3) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc cs t rc cke bs1 dqm ras cas bs0 t rcd raa a0~a9, a11, a12 dq active read bank#0 bank#2 bank#3 bank#1 idle we aw0 aw1 aw2 aw3 t ac cax bx0 bx1 bx2 bx3 t ac raa caw rab rab active read ap * * : ap shows the internal precharge start timing. note): see figure 15 ap * t rcd t rp t ras t ras t rp a10 cas tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 24/49 figure 10. auto precharge write (burst length = 4) a0~a9, a11, a12 clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t rc cke bs1 dqm ras cas bs0 a10 t rcd raa dq active write bank#0 bank#2 bank#3 bank#1 idle we aw0 aw1 aw2 aw3 raa caw rab rab ap * * : ap shows the internal precharge start timing. note): see figure 16 ap * t rcd t rp t ras t ras cax rac rac bx0 bx2 bx3 bx1 active write active t rc t rp tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 25/49 figure 11. auto refresh cycle clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc cs ras cas bs0, bs1 we cke dqm a10 a0~a9, a11, a12 dq all banks precharge auto refresh auto refresh (arbitrary cycle) t rp t rc tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 26/49 figure 12. self refresh cycle clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs ras cas bs0, bs1 we cke dqm a10 a0~a9, a11, a12 dq all banks precharge self refresh entry arbitrary cycle t cks t sb t cks no operation cycle t cks t rp t rc self refresh exit tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 27/49 figure 13. power down mode a0~a9, a11, a12 clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs cke dqm ras cas bs a10 raa dq active we raa caa note): the power down mode is invoked by asserting cke ?low?. all input/output buffers (except the cke buffer) are turned off in power down mode. when cke goes high, the no-operation command input must be at next clk rising edge and cke should be set high at least 1clk + t cks at power down mode exit. active ax0 ax2 ax1 ax3 cax raa raa nop precharge & power down mode entry nop t cks t sb t cks power down mode exit t cks t sb t cks power down mode entry power down mode exit tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 28/49 figure 14. burst read and single write (burst length = = tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 29/49 pin functions clock input: clk 7kh &/. lqsxw lv xvhg dv wkh uhihuhqfh iru 6'5$0 rshudwlrqv 2shudwlrqv duh v\qfkurql]hg wr wkh srvlwlyh hgjhv ri &/. clock enable: cke 7kh &.( lqsxw lv xvhg wr vxvshqg wkh lqwhuqdo &/. :khq wkh &.( vljqdo lv dvvhuwhg orz wkh lqwhuqdo &/. lv vxvshqghg dqg rxwsxw gdwd lv khog lqwdfw zkloh &.( lv dvvhuwhg orz :khq wkh ghylfh lv qrw uxqqlqj d %xuvw f\foh wkh &.( lqsxw frqwurov wkh hqwu\ wr wkh 3rzhu 'rzq dqg 6hoi 5hiuhvk prghv :khq wkh 6hoi 5hiuhvk frppdqg lv lvvxhg wkh ghylfh pxvw eh lq wkh lgoh vwdwh bank select: bs0, bs1 7kh 7& 60 $)7$)7/ 7& 60 $)7$)7/ dqg wkh 7& 60 $)7$)7/ duh rujdql]hg dv irxuedqn phpru\ fhoo duud\v 7kh %6 %6 lqsxwv duh odwfkhg dw wkh wlph ri dvvhuwlrq ri wkh rshudwlrq frppdqgv dqg vhohfwv wkh edqn wr eh xvhg iru wkh rshudwlrq bs0 bs1 0 0 bank#0 1 0 bank#1 0 1 bank#2 1 1 bank#3 address inputs: a0~a12 7kh $a$ lqsxwv duh dgguhvv wr dffhvv wkh phpru\ fhoo duud\ dv iroorzlqj wdeoh row address column address tc59sm916aft/aftl a0~a12 a0~a9 tc59sm908aft/aftl a0~a12 a0~a9, a11 tc59sm904aft/aftl a0~a12 a0~a9, a11, a12 7kh urz dgguhvv elwv duh odwfkhg dw wkh %dqn $fwlydwh frppdqg dqg froxpq dgguhvv elwv duh odwfkhg rq wkh 5hdg ru :ulwh frppdqg $ovr wkh $a$ lqsxwv duh xvhg wr vhw wkh gdwd lq wkh 0rgh uhjlvwhu lq d 0rgh 5hjlvwhu 6hw f\foh tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 30/49 chip select: 7kh &6 lqsxw frqwurov wkh odwfklqj ri wkh frppdqgv rq wkh srvlwlyh hgjhv ri &/. zkhq &6 lv dvvhuwhg orz 1r frppdqgv duh odwfkhg dv orqj dv &6 lv khog kljk row address strobe: 7kh 5$6 lqsxw ghilqhv wkh rshudwlrq frppdqgv lq frqmxqfwlrq zlwk wkh &$6 dqg :( lqsxwv dqg lv odwfkhg dw wkh srvlwlyh hgjhv ri &/. :khq 5$6 dqg &6 duh dvvhuwhg orz dqg &$6 lv dvvhuwhg kljk hlwkhu wkh %dqn $fwlydwh frppdqg ru wkh 3uhfkdujh frppdqg lv vhohfwhg e\ wkh :( vljqdo :khq :( lv dvvhuwhg kljk wkh %dqn $fwlydwh frppdqg lv vhohfwhg dqg wkh edqn ghvljqdwhg e\ %6 %6 duh wxuqhg rq vr wkdw lw lv lq wkh dfwlyh vwdwh :khq :( lv dvvhuwhg orz wkh 3uhfkdujh frppdqg lv vhohfwhg dqg wkh edqn ghvljqdwhg e\ %6 %6 duh vzlwfkhg wr wkh lgoh vwdwh diwhu 3uhfkdujh rshudwlrq column address strobe: 7kh &$6 lqsxw ghilqhv wkh rshudwlrq frppdqgv lq frqmxqfwlrq zlwk wkh 5$6 dqg :( lqsxwv dqg lv odwfkhg dw wkh srvlwlyh hgjhv ri &/. :khq 5$6 lv khog kljk dqg &6 lv dvvhuwhg orz froxpq dffhvv lv vwduwhg e\ dvvhuwlqj &$6 orz 7khq wkh 5hdg ru :ulwh frppdqg lv vhohfwhg e\ dvvhuwlqj :( orz ru kljk write enable: 7kh :( lqsxw ghilqhv wkh rshudwlrq frppdqgv lq frqmxqfwlrq zlwk wkh 5$6 dqg &$6 lqsxwv dqg lv odwfkhg dw wkh srvlwlyh hgjhv ri &/. 7kh :( lqsxw lv xvhg wr vhohfw wkh %dqn $fwlydwh ru 3uhfkdujh frppdqg dqg 5hdg ru :ulwh frppdqg data input/output mask: dqm or ldqm and udqm 7kh '40 lqsxw hqdeohv rxwsxw lq d 5hdg f\foh dqg ixqfwlrqv dv wkh lqsxw gdwd pdvn lq d :ulwh f\foh :khq '40 lv dvvhuwhg kljk dw wkh srvlwlyh hgjhv ri &/. rxwsxw gdwd lv glvdeohg diwhu wzr forfn f\fohv gxulqj d 5hdg f\foh dqg lqsxw gdwd lv pdvnhg dw wkh vdph forfn f\foh gxulqj d :ulwh f\foh ,q wkh fdvh ri wkh 7& 60 $)7$)7/ wkh /'40 dqg 8'40 lqsxwv ixqfwlrq dv e\wh gdwd frqwuro 7kh /'40 lqsxw fdq frqwuro '4a'4 lq d 5hdg ru :ulwh f\foh dqg wkh 8'40 fdq frqwuro '4a'4 lq d 5hdg ru :ulwh f\foh data input/output: dq0~dq15 7kh '4a'4 lqsxw dqg rxwsxw gdwd duh v\qfkurql]hg zlwk wkh srvlwlyh hgjhv ri &/. ,q wkh fdvh ri 7& 60 $)7$)7/ dqg 7& 60 $)7$)7/ wkhvh slqv duh '4a'4 dqg '4a'4 uhvshfwlyho\ cs ras cas we tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 31/49 operation mode 7deoh vkrzv wkh wuxwk wdeoh iru wkh rshudwlrq frppdqgv table 1. truth table (note (1) and (2) ) command device state cke n-1 cke n dqm (5) bs0, bs1 a10 a12, a11, a9~a0 cs ras cas we bank activate idle (3) hx x vvvllhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) hx x vlvlhll write with auto precharge active (3) hx x vhvlhll read active (3) hx x vlvlhlh read with auto precharge active (3) hx x vhvlhlh mode register set idle h x x v v v l l l l no-operation any h x x x x x l h h h burst stop active (4) hxxxxxlhhl device deselect any h x x x x x h x x x auto-refresh idle h h x x x x l l l h self-refresh entry idle h l x x x x l l l h hxxx self-refresh exit idle (self refresh) lh x xxx lhhx clock suspend mode entry active h l x x x x x x x x hxxx power down mode entry idle/active (6) hl x xxx lhhx clock suspend mode exit active l h x x x x x x x x hxxx power down mode exit any (power down) lh x xxx lhhx data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x note 1. v = valid, x = don?t care, l = low level, h = high level 2. cke n signal is input level when commands are issued. cke n-1 signal is input level one clock cycle before the commands are issued. 3. these are state designated by the bs0, bs1 signals. 4. device state is full page burst operation. 5. ldqm, udqm (tc59sm916aft/aftl) 6. power down mode can not entry in the burst cycle. when this command assert in the burst cycle, device state is clock suspend mode. tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 32/49 1. command function %dqn $fwlydwh frppdqg 5$6 = / &$6 = + :( = + %6 %6 = %dqn $a$ = 5rz $gguhvv 7kh %dqn $fwlydwh frppdqg dfwlydwhv wkh edqn ghvljqdwhg e\ wkh %6 %dqn 6hohfw vljqdo 5rz dgguhvvhv duh odwfkhg rq $a$ zkhq wklv frppdqg lv lvvxhg dqg wkh fhoo gdwd lv uhdg rxw wr wkh vhqvh dpsolilhuv 7kh pd[lpxp wlph wkdw hdfk edqn fdq eh khog lq wkh dfwlyh vwdwh lv vshflilhg dv w 5$6 pd[ %dqn 3uhfkdujh frppdqg 5$6 = / &$6 = + :( = / %6 %6 = %dqn $ = / $a$ $ $ = 'rqw fduh 7kh %dqn 3uhfkdujh frppdqg suhfkdujhv wkh edqn ghvljqdwhg e\ %6 7kh suhfkdujhg edqn lv vzlwfkhg iurp wkh dfwlyh vwdwh wr wkh lgoh vwdwh 3uhfkdujh $oo frppdqg 5$6 = / &$6 = + :( = / %6 %6 = 'rqw fduh $ = + $a$ $ $ = 'rqw fduh 7kh 3uhfkdujh $oo frppdqg suhfkdujhv doo edqnv vlpxowdqhrxvo\ $oo edqnv duh wkhq vzlwfkhg wr wkh lgoh vwdwh :ulwh frppdqg 5$6 = + &$6 = / :( = / %6 %6 = %dqn $ = / $a$ $ $ = &roxpq $gguhvv 7kh :ulwh frppdqg shuirupv d :ulwh rshudwlrq wr wkh edqn ghvljqdwhg e\ %6 dqg %6 7kh zulwh gdwd lv odwfkhg dw wkh srvlwlyh hgjhv ri &/. 7kh ohqjwk ri wkh zulwh gdwd %xuvw /hqjwk dqg froxpq dffhvv vhtxhqfh $gguhvvlqj 0rgh pxvw eh surjudpphg lq wkh 0rgh 5hvlvwhu dw srzhuxs sulru wr wkh :ulwh rshudwlrq 7kh $ lqsxw lv 'rqw fduh rq wkh 7& 60 $)7$)7/ dqg wkh $ dqg $ lqsxwv duh 'rqw fduh rq wkh 7& 60 $)7$)7/ :ulwh zlwk $xwr 3uhfkdujh frppdqg 5$6 = + &$6 = / :( = / %6 %6 = %dqn $ = + $a$ $ $ = &roxpq $gguhvv 7kh :ulwh zlwk $xwr 3uhfkdujh frppdqg shuirupv wkh 3uhfkdujh rshudwlrq dxwrpdwlfdoo\ diwhu wkh :ulwh rshudwlrq 7kh lqwhuqdo suhfkdujh vwduwv lq wkh f\fohv lpphgldwho\ iroorzlqj wkh f\foh lq zklfk wkh odvw gdwd lv zulwwhq lqghshqghqw ri &$6 /dwhqf\ )ljxuh 7klv frppdqg pxvw qrw eh lqwhuuxswhg e\ dq\ rwkhu frppdqgv 7kh $ lqsxw lv 'rqw fduh dw wkh 7& 60 $)7$)7/ dqg wkh $ dqg $ lqsxwv duh 'rqw fduh rq wkh 7& 60 $)7$)7/ 5hdg frppdqg 5$6 = + &$6 = / :( = + %6 %6 = %dqn $ = / $a$ $ $ = &roxpq $gguhvv 7kh 5hdg frppdqg shuirupv d 5hdg rshudwlrq wr wkh edqn ghvljqdwhg e\ %6 7kh uhdg gdwd lv lvvxhg vhtxhqwldoo\ v\qfkurql]hg wr wkh srvlwlyh hgjhv ri &/. 7kh ohqjwk ri uhdg gdwd %xuvw /hqjwk $gguhvvlqj 0rgh dqg &$6 /dwhqf\ dffhvv wlph iurp &$6 frppdqg lq d forfn f\foh pxvw eh surjudpphg lq wkh 0rgh 5hjlvwhu dw srzhuxs sulru wr wkh :ulwh rshudwlrq 7kh $ lqsxw lv 'rqw fduh rq wkh 7& 60 $)7$)7/ dqg wkh $ dqg $ lqsxwv duh 'rqw fduh rq wkh 7& 60 $)7$)7/ tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 33/49 5hdg zlwk $xwr 3uhfkdujh frppdqg 5$6 = + &$6 = / :( = + %6 %6 = %dqn $ = + $a$ $ $ = &roxpq $gguhvv 7kh 5hdg zlwk $xwr 3uhfkdujh frppdqg dxwrpdwlfdoo\ shuirupv wkh 3uhfkdujh rshudwlrq diwhu wkh 5hdg rshudwlrq :khq wkh &$6 /dwhqf\ = wkh lqwhuqdo suhfkdujh vwduwv wzr f\fohv ehiruh wkh odvw gdwd lv rxwsxw :khq wkh &$6 /dwhqf\ = wkh lqwhuqdo suhfkdujh vwduwv rqh f\foh ehiruh wkh odvw gdwd lv rxwsxw )ljxuh 7klv frppdqg pxvw qrw eh lqwhuuxswhg e\ dq\ rwkhu frppdqg 7kh $ lqsxw lv 'rqw fduh rq wkh 7& 60 $)7$)7/ dqg wkh $ dqg $ lqsxwv duh 'rqw fduh rq wkh 7& 60 $)7$)7/ 0rgh 5hjlvwhu 6hw frppdqg 5$6 = / &$6 = / :( = / %6 %6 $a$ = 5hjlvwhu 'dwd 7kh 0rgh 5hjlvwhu 6hw frppdqg surjudpv wkh ydoxhv ri &$6 odwhqf\ $gguhvvlqj 0rgh dqg %xuvw /hqjwk lq wkh 0rgh 5hjlvwhu 7kh ghidxow ydoxhv lq wkh 0rgh 5hjlvwhu diwhu srzhuxs duh xqghilqhg wkhuhiruh wklv frppdqg pxvw eh lvvxhg gxulqj wkh srzhuxs vhtxhqfh $ovr wklv frppdqg fdq eh lvvxhg zkloh doo edqnv duh lq wkh lgoh vwdwh 1r2shudwlrq frppdqg 5$6 = + &$6 = + :( = + 7kh 1r2shudwlrq frppdqg vlpso\ shuirupv qr rshudwlrq %xuvw vwrs frppdqg 5$6 = + &$6 = + :( = / 7kh %xuvw vwrs frppdqg lv xvhg wr vwrs wkh exuvw rshudwlrq 7klv frppdqg lv ydolg gxulqj d )xoo 3djh %xuvw rshudwlrq 'xulqj rwkhu w\shv ri %xuvw rshudwlrq wkh frppdqg lv loohjdo 'hylfh 'hvhohfw frppdqg &6 = + 7kh 'hylfh 'hvhohfw frppdqg glvdeohv wkh frppdqg ghfrghu vr wkdw wkh 5$6 &$6 :( dqg $gguhvv lqsxwv duh ljqruhg 7klv frppdqg lv vlplodu wr wkh 1r2shudwlrq frppdqg $xwr 5hiuhvk frppdqg 5$6 = / &$6 = / :( = + &.( = + %6 %6 $a$ = 'rqw fduh 7kh $xwr 5hiuhvk frppdqg lv xvhg wr uhiuhvk wkh urz dgguhvv surylghg e\ wkh lqwhuqdo uhiuhvk frxqwhu 7kh 5hiuhvk rshudwlrq pxvw eh shuiruphg wlphv zlwklq pv 7kh qh[w frppdqg fdq eh lvvxhg diwhu w 5& iurp wkh hqg ri wkh $xwr 5hiuhvk frppdqg :khq wkh $xwr 5hiuhvk frppdqg lv lvvxhg $oo edqnv pxvw eh lq wkh lgoh vwdwh 7kh $xwr 5hiuhvk rshudwlrq lv htxlydohqw wr wkh &$6 ehiruh 5$6 rshudwlrq lq d frqyhqwlrqdo '5$0 tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 34/49 6hoi 5hiuhvk (qwu\ frppdqg 5$6 = / &$6 = / :( = + &.( = / %6 %6 $a$ = 'rqw fduh 7kh 6hoi 5hiuhvk (qwu\ frppdqg lv xvhg wr hqwhu 6hoi 5hiuhvk prgh :kloh wkh ghylfh lv lq 6hoi 5hiuhvk prgh doo lqsxw dqg rxwsxw exiihuv h[fhsw wkh &.( exiihu duh glvdeohg dqg wkh 5hiuhvk rshudwlrq lv dxwrpdwlfdoo\ shuiruphg 6hoi 5hiuhvk prgh lv h[lwhg e\ wdnlqj &.( kljk wkh 6hoi 5hiuhvk ([lw frppdqg 6hoi 5hiuhvk ([lw frppdqg &.( = + &6 = +ru&.( = + 5$6 = + &$6 = + 7klv frppdqg lv xvhg wr h[lw iurp 6hoi 5hiuhvk prgh $q\ vxevhtxhqw frppdqgv fdq eh lvvxhg diwhu w 5& iurp wkh hqg ri wklv frppdqg &orfn 6xvshqg 0rgh (qwu\3rzhu 'rzq 0rgh (qwu\ frppdqg &.( = / 7kh lqwhuqdo &/. lv vxvshqghg iru rqh f\foh zkhq wklv frppdqg lv lvvxhg zkhq &.( lv dvvhuwhg orz 7kh ghylfh vwdwh lv khog lqwdfw zkloh wkh &/. lv vxvshqghg 2q wkh rwkhu kdqg zkhq wkh ghylfh lv qrw rshudwlqj wkh %xuvw f\foh wklv frppdqg shuirupv hqwu\ lqwr 3rzhu 'rzq prgh $oo lqsxw dqg rxwsxw exiihuv h[fhsw wkh &.( exiihu duh wxuqhg rii lq 3rzhu 'rzq prgh &orfn 6xvshqg 0rgh ([lw3rzhu 'rzq 0rgh ([lw frppdqg &.( = + :khq wkh lqwhuqdo &/. kdv ehhq vxvshqghg rshudwlrq ri wkh lqwhuqdo &/. lv uhvxphg e\ surylglqj wklv frppdqg dvvhuwlqj &.( kljk :khq wkh ghylfh lv lq 3rzhu 'rzq prgh wkh ghylfh h[lwv wklv prgh dqg doo glvdeohg exiihuv duh wxuqhg rq wr wkh dfwlyh vwdwh $q\ v xevhtxhqw frppdqgv fdq eh lvvxhg diwhu rqh forfn f\foh iurp wkh hqg ri wklv frppdqg 'dwd :ulwh2xwsxw (qdeoh 'dwd 0dvn2xwsxw 'lvdeoh frppdqg '40 = /+ ru /'40 8'40 = /+ 'xulqj d :ulwh f\foh wkh '40 ru /'40 8'40 vljqdo ixqfwlrqv dv 'dwd 0dvn dqg fdq frqwuro hyhu\ zrug ri wkh lqsxw gdwd 'xulqj d 5hdg f\foh wkh '40 ru /'40 8'40 vljqdo ixqfwlrqv dv wkh frqwuro ri rxwsxw exiihuv 7kh /'40 vljqdo frqwurov '4a'4 dqg wkh 8'40 vljqdo frqwurov '4a'4 tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 35/49 2. read operation ,vvxlqj wkh %dqn $fwlydwh frppdqg wr wkh lgoh edqn sxwv lw lqwr wkh dfwlyh vwdwh :khq wkh 5hdg frppdqg lv lvvxhg diwhu w 5&' iurp wkh %dqn $fwlydwh frppdqg wkh gdwd lv uhdg rxw vhtxhqwldoo\ v\qfkurql]hg wr wkh srvlwlyh hgjhv ri &/. d %xuvw 5hdg rshudwlrq 7kh lqlwldo uhdg gdwd ehfrphv dydlodeoh diwhu &$6 /dwhqf\ iurp wkh lvvxlqj ri wkh 5hdg frppdqg 7kh &$6 odwhqf\ pxvw eh vhw lq wkh 0rgh 5hjlvwhu dw srzhuxs ,q dgglwlrq wkh exuvw ohqjwk ri uhdg gdwd dqg $gguhvvlqj 0rgh pxvw eh vhw (dfk edqn lv khog lq wkh dfwlyh vwdwh xqohvv wkh 3uhfkdujh frppdqg lv lvvxhg vr wkdw wkh vhqvh dpsolilhuv fdq eh xvhg dv vhfrqgdu\ fdfkh :khq wkh 5hdg zlwk $xwr 3uhfkdujh frppdqg lv lvvxhg wkh 3uhfkdujh rshudwlrq lv shuiruphg dxwrpdwlfdoo\ diwhu wkh 5hdg f\foh wkhq wkh edqn lv vzlwfkhg wr wkh lgoh vwdwh 7klv frppdqg fdqqrw eh lqwhuuxswhg e\ dq\ rwkhu frppdqgv $ovr zkhq wkh %xuvw /hqjwk lv dqg w 5&' plq wkh wlplqj iurp wkh 5$6 frppdqg wr wkh vwduw ri wkh $xwr 3uhfkdujh rshudwlrq lv vkruwhu wkdq w 5$6 plq ,q wklv fdvh w 5$6 plq pxvw eh vdwlvilhg e\ h[whqglqj w 5&' )ljxuh :khq wkh 3uhfkdujh rshudwlrq lv shuiruphg rq d edqn gxulqj d %xuvw 5hdg rshudwlrq wkh %xuvw rshudwlrq lv whuplqdwhg )ljxuh :khq wkh %xuvw /hqjwk lv ixoosdjh froxpq gdwd lv uhshdwhgo\ uhdg rxw xqwlo wkh %xuvw 6wrs frppdqg ru 3uhfkdujh frppdqg lv lvvxhg 3. write operation ,vvxlqj wkh :ulwh frppdqg diwhu w 5&' iurp wkh %dqn $fwlydwh frppdqg wkh lqsxw gdwd lv odwfkhg vhtxhqwldoo\ v\qfkurql]lqj zlwk wkh srvlwlyh hgjhv ri &/. diwhu wkh :ulwh frppdqg %xuvw :ulwh rshudwlrq 7kh exuvw ohqjwk ri wkh :ulwh gdwd %xuvw /hqjwk dqg $gguhvvlqj 0rgh pxvw eh vhw lq wkh 0rgh 5hjlvwhu dw srzhuxs :khq wkh :ulwh zlwk $xwr 3uhfkdujh frppdqg lv lvvxhg wkh 3uhfkdujh rshudwlrq lv shuiruphg dxwrpdwlfdoo\ diwhu wkh :ulwh f\foh wkhq wkh edqn lv vzlwfkhg wr wkh lgoh vwdwh 7klv frppdqg fdqqrw eh lqwhuuxswhg e\ dq\ rwkhu frppdqg iru wkh hqwluh exuvw gdwd gxudwlrq $ovr zkhq wkh %xuvw /hqjwk lv dqg w 5&' plq wkh wlplqj iurp wkh 5$6 frppdqg wr wkh vwduw ri wkh $xwr 3uhfkdujh rshudwlrq lv vkruwhu wkdq w 5$6 plq ,q wklv fdvh w 5$6 plq pxvw eh vdwlvilhg e\ h[whqglqj w 5&' )ljxuh :khq wkh 3uhfkdujh rshudwlrq lv shuiruphg lq d edqn gxulqj d %xuvw :ulwh rshudwlrq wkh %xuvw rshudwlrq lv whuplqdwhg )ljxuh :khq wkh %xuvw /hqjwk lv ixoosdjh wkh lqsxw gdwd lv uhshdwhgo\ odwfkhg xqwlo wkh %xuvw 6wrs frppdqg ru wkh 3uhfkdujh frppdqg lv lvvxhg :khq wkh %xuvw 5hdg dqg 6lqjoh :ulwh prgh lv vhohfwhg wkh zulwh exuvw ohqjwk lv uhjdugohvv ri wkh uhdg exuvw ohqjwk tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 36/49 4. precharge 7khuh duh wzr frppdqgv zklfk shuirup wkh 3uhfkdujh rshudwlrq %dqn 3uhfkdujh dqg 3uhfkdujh $oo :khq wkh %dqn 3uhfkdujh frppdqg lv lvvxhg wr wkh dfwlyh edqn wkh edqn lv suhfkdujhg dqg wkhq vzlwfkhg wr wkh lgoh vwdwh 7kh %dqn 3uhfkdujh frppdqg fdq suhfkdujh rqh edqn lqghshqghqwo\ ri wkh rwkhu edqn dqg krog wkh xqsuhfkdujhg edqn lq wkh dfwlyh vwdwh 7kh pd[lpxp wlph hdfk edqn fdq eh khog lq wkh dfwlyh vwdwh lv vshflilhg dv w 5$6 pd[ 7khuhiruh hdfk edqn pxvw eh suhfkdujhg zlwklq w 5$6 pd[ iurp wkh %dqn $fwlydwh frppdqg 7kh 3uhfkdujh $oo frppdqg fdq eh xvhg wr suhfkdujh doo edqnv vlpxowdqhrxvo\ (yhq li edqnv duh qrw lq wkh dfwlyh vwdwh wkh 3uhfkdujh $oo frppdqg fdq vwloo eh lvvxhg ,q wklv fdvh wkh 3uhfkdujh rshudwlrq lv shuiruphg rqo\ iru wkh dfwlyh edqn dqg wkh suhfkdujhg edqn lv wkhq vzlwfkhg wr wkh lgoh vwdwh 5. page mode 7kh 5hdg ru :ulwh frppdqg fdq eh lvvxhg rq dq\ forfn f\foh :khqhyhu d 5hdg rshudwlrq lv wr eh lqwhuuxswhg e\ d :ulwh frppdqg wkh rxwsxw gdwd pxvw eh pdvnhg e\ '40 wr dyrlg ,2 frqiolfw $ovr zkhq d :ulwh rshudwlrq lv wr eh lqwhuuxswhg e\ d 5hdg frppdqg rqo\ wkh lqsxw gdwd ehiruh wkh 5hdg frppdqg lv hqdeoh dqg wkh lqsxw gdwd diwhu wkh 5hdg frppdqg lv glvdeohg 6. burst termination :khq wkh 3uhfkdujh frppdqg lv lvvxhg iru d edqn lq d %xuvw f\foh wkh %xuvw rshudwlrq lv whuplqdwhg :khq wkh %xuvw 5hdg f\foh lv lqwhuuxswhg e\ wkh 3uhfkdujh frppdqg uhdg rshudwlrq lv glvdeohg diwhu forfn f\foh ri &$6 odwhqf\ iurp wkh 3uhfkdujh frppdqg )ljxuh :khq wkh %xuvw :ulwh f\foh lv lqwhuuxswhg e\ wkh 3uhfkdujh frppdqg wkh lqsxw flufxlw lv uhvhw dw wkh vdph forfn f\foh dw zklfk wkh 3uhfkdujh frppdqg lv lvvxhg ,q wklv fdvh wkh '40 vljqdo pxvw eh dvvhuwhg +ljk wr suhyhqw zulwlqj wkh lqydolg gdwd wr wkh fhoo duud\ )ljxuh :khq wkh %xuvw 6wrs frppdqg lv lvvxhg iru wkh edqn lq d )xoosdjh %xuvw f\foh wkh %xuvw rshudwlrq lv whuplqdwhg :khq wkh %xuvw 6wrs frppdqg lv lvvxhg gxulqj )xoosdjh %xuvw 5hdg f\foh uhdg rshudwlrq lv glvdeohg diwhu forfn f\foh ri &$6 odwhqf\ iurp wkh %xuvw 6wrs frppdqg :khq wkh %xuvw 6wrs frppdqg lv lvvxhg gxulqj d )xoosdjh %xuvw :ulwh f\foh zulwh rshudwlrq lv glvdeohg dw wkh vdph forfn f\foh dw zklfk wkh %xuvw 6wrs frppdqg lv lvvxhg )ljxuh tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 37/49 7. mode register operation 7kh 0rgh uhjlvwhu ghvljqdwhv wkh rshudwlrq prgh iru wkh 5hdg ru :ulwh f\foh 7klv uhjlvwhu lv glylghg lqwr wkuhh ilhogv $ %xuvw /hqjwk ilhog wr vhw wkh ohqjwk ri exuvw gdwd dq $gguhvvlqj 0rgh vhohfwhg elwv wr ghvljqdwh wkh froxpq dffhvv vhtxhqfh lq d %xuvw f\foh dqg d /dwhqf\ ilhog wr vhw wkh dffhvv wlph lq forfn f\foh 7kh 0rgh 5hjlvwhu lv surjudpphg e\ wkh 0rgh 5hjlvwhu 6hw frppdqg zkhq doo edqnv duh lq wkh lgoh vwdwh 7kh gdwd wr eh vhw lq wkh 0rgh 5hjlvwhu lv wudqvihuuhg xvlqj wkh $a$ %6 %6 lqsxwv 7kh lqlwldo ydoxh ri wkh 0rgh 5hjlvwhu diwhu srzhuxs lv xqghilqhg wkhuhiruh wkh 0rgh 5hjlvwhu 6hw frppdqg pxvw eh lvvxhg ehiruh surshu rshudwlrq ? %xuvw /hqjwk ilhog $a$ 7klv ilhog vshflilhv wkh gdwd ohqjwk iru froxpq dffhvv xvlqj wkh $a$ slqv dqg vhwv wkh %xuvw /hqjwk wr eh zrugv ru ixoosdjh a2 a1 a0 burst length 0001 word 0012 words 0104 words 0118 words 1 1 1 full-page ? $gguhvvlqj 0rgh 6hohfw $ 7kh $gguhvvlqj 0rgh fdq eh rqh ri wzr prghv ,qwhuohdyh prgh ru 6htxhqwldo prgh :khq wkh $ elw lv 6htxhqwldo prgh lv vhohfwhg :khq wkh $ elw lv ,qwhuohdyh prgh lv vhohfwhg %rwk $gguhvvlqj prghv vxssruw exuvw ohqjwk ri dqg zrugv $gglwlrqdoo\ 6htxhqwldo prgh vxssruwv wkh ixoosdjh exuvw a3 addressing mode 0 sequential 1 interleave &$6 tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 38/49 ? $gguhvvlqj vhtxhqfh ri 6htxhqwldo prgh $ froxpq dffhvv lv shuiruphg e\ lqfuhphqwlqj wkh froxpq dgguhvv lqsxw wr wkh ghylfh 7kh dgguhvv lv ydulhg e\ wkh %xuvw /hqjwk dv vkrzq lq 7deoh table 2. addressing sequence for sequential mode data access address burst length data0 n data1 n + 1 data2 n + 2 data3 n + 3 data4 n + 4 data5 n + 5 data6 n + 6 data7 n + 7 2 words (address bits is a0) not carried from a0 to a1 4 words (address bits is a1, a0) not carried from a1 to a2 8 words (address bits is a2, a1, a0) not carried from a2 to a3 ? $gguhvvlqj vhtxhqfh ri ,qwhuohdyh prgh $ froxpq dffhvv lv vwduwhg iurp wkh lqsxw froxpq dgguhvv dqg lv shuiruphg e\ lqyhuwlqj wkh dgguhvv elwv lq wkh vhtxhqfh vkrzq lq 7deoh table 3. addressing sequence for interleave mode data access address burst length data0 a8a7a6a5a4a3a2a1a0 data1 a8a7a6a5a4a3a2a1 0 a data2 a8a7a6a5a4a3a2 1 aa0 data3 a8a7a6a5a4a3a2 1 a 0 a data4 a8a7a6a5a4a3 2 aa1a0 data5 a8a7a6a5a4a3 2 aa1 0 a data6 a8a7a6a5a4a3 2 a 1 aa0 data7 a8a7a6a5a4a3 2 a 1 a 0 a 2 words 4 words 8 words tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 39/49 addressing sequence example (burst length = 8 and input address is 13.) interleave mode sequential mode data a8 a7 a6 a5 a4 a3 a2 a1 a0 add add data0 00000110113 13 13 data1 0000011001213 + 114 data2 0000011111513 + 215 data3 0000011101413 + 38 data4 000001001913 + 49 data5 000001000813 + 510 data6 0000010111113 + 611 data7 0000010101013 + 712 calculated using a2, a1 and a0 bits not carry from a2 to a3 bit. ? &$6 /dwhqf\ ilhog $a$ 7klv ilhog vshflilhv wkh qxpehu ri forfn f\fohv iurp wkh dvvhuwlrq ri wkh 5hdg frppdqg wr wkh iluvw gdwd uhdg 7kh plqlpxp ydoxhv ri &$6 /dwhqf\ ghshqgv rq wkh iuhtxhqf\ ri &/. 7kh plqlpxp ydoxh zklfk vdwlvilhv wkh iroorzlqj irupxod pxvw eh vhw lq wklv ilhog a6 a5 a4 cas latency 0102 clock 0113 clock ? 7hvw prgh hqwu\ elw $ 7klv elw lv xvhg wr hqwhu 7hvw prgh dqg pxvw eh vhw wr iru qrupdo rshudwlrq ? 5hvhuyhg elwv $ $ $ $ %6 %6 7khvh elwv duh uhvhuyhg iru ixwxuh rshudwlrqv 7kh\ pxvw eh vhw wr iru qrupdo rshudwlrq ? 6lqjoh :ulwh prgh $ 7klv elw lv xvhg wr vhohfw wkh zulwh prgh :khq wkh $ elw lv %xuvw 5hdg dqg %xuvw :ulwh prgh duh vhohfwhg :khq wkh $ elw lv %xuvw 5hdg dqg 6lqjoh :ulwh prgh duh vhohfwhg a9 write mode 0 burst read and burst write 1 burst read and single write read cycle cas latency = 3 command read 13 01234567891011 dq0~dq7 q0 q1 q2 q3 q4 q5 q6 q7 address data address i nterleave mode 13 12 15 14 9 8 11 10 13 14 15 8 9 10 11 12 s equential mode tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 40/49 8. refresh operation 7zr w\shv ri 5hiuhvk rshudwlrq fdq eh shuiruphg rq wkh ghylfh $xwr 5hiuhvk dqg 6hoi 5hiuhvk $xwr 5hiuhvk lv vlplodu wr wkh &$6 ehiruh 5$6 uhiuhvk ri frqyhqwlrqdo '5$0v dqg lv shuiruphg e\ lvvxlqj wkh $xwr 5hiuhvk frppdqg zkloh doo edqnv duh lq wkh lgoh vwdwh %\ uhshdwlqj wkh $xwr 5hiuhvk f\foh doo edqnv uhiuhvkhg dxwrpdwlfdoo\ 7kh 5hiuhvk rshudwlrq pxvw eh shuiruphg wlphv urzv zlwklq pv )ljxuh 7kh shulrg ehwzhhq wkh $xwr 5hiuhvk frppdqg dqg wkh qh[w frppdqg lv vshflilhg e\ w 5& 6hoi 5hiuhvk prgh lv hqwhuhg e\ lvvxlqj wkh 6hoi 5hiuhvk frppdqg &.( dvvhuwhg orz zkloh doo edqnv duh lq wkh lgoh vwdwh 7kh ghylfh lv lq 6hoi 5hiuhvk prgh iru dv orqj dv &.( lv khog orz ,q 6hoi 5hiuhvk prgh doo lqsxwrxwsxw exiihuv h[fhsw wkh &.( exiihu duh glvdeohg wr orzhu srzhu glvvlsdwlrq )ljxuh ,q wkh fdvh ri exuvw $xwr 5hiuhvk frppdqgv exuvw $xwr 5hiuhvk frppdqgv pxvw eh shuiruphg zlwklq v ehiruh hqwhulqj dqg diwhu h[lwlqj wkh 6hoi 5hiuhvk prgh ,q wkh fdvh ri glvwulexwhg $xwr 5hiuhvk frppdqgv glvwulexwhg $xwr 5hiuhvk frppdqgv pxvw eh lvvxhg hyhu\ v dqg wkh odvw glvwulexwhg $xwr 5hiuhvk frppdqg pxvw eh shuiruphg zlwklq v ehiruh hqwhulqj wkh 6hoi 5hiuhvk prgh $iwhu h[lwlqj iurp wkh 6hoi 5hiuhvk prgh wkh uhiuhvk rshudwlrq pxvw eh shuiruphg zlwklq v 9. power down mode :khq wkh ghylfh hqwhuv wkh 3rzhu 'rzq prgh doo lqsxwrxwsxw exiihuv h[fhsw &.( exiihu duh glvdeohg wr orzhu srzhu glvvlsdwlrq lq wkh lgoh vwdwh 3rzhu 'rzq prgh lv hqwhuhg e\ dvvhuwlqj &.( orz zkloh wkh ghylfh lv qrw uxqqlqj d %xuvw f\foh 7dnlqj &.( kljk h[lw wklv prgh :khq &.( jrhv kljk d 1rrshudwlrq frppdqg pxvw eh lqsxw dw qh[w &/. ulvlqj hgjh ri &/. )ljxuh dqg &.( vkrxog eh vhw kljk dw ohdvw &/. + w &.6 dw 3rzhu 'rzq 0rgh ([lw 10. clk suspension and input/output mask :khq wkh ghylfh lv uxqqlqj d %xuvw f\foh wkh lqwhuqdo &/. lv vxvshqghg e\ dvvhuwlqj &.( orz wkh exuvw rshudwlrq lv iur]hq iurp wkh qh[w f\foh $ 5hdg:ulwh rshudwlrq lv khog lqwdfw xqwlo wkh &.( vljqdo lv wdnhq kljk 7kh 2xwsxw 'lvdeoh:ulwh 0dvn vljqdo '40 kdv wzr ixqfwlrqv frqwuroolqj wkh rxwsxw gdwd lq d 5hdg f\foh dqg shuiruplqj zrug pdvn lq d :ulwh f\foh :khq wkh '40 lv dvvhuwhg kljk dw wkh srvlwlyh hgjh ri &/. wkh rxwsxw gdwd lv glvdeohg diwhu wzr forfn f\fohv lq wkh fdvh ri d 5hdg rshudwlrq dqg wkh zulwh gdwd lv pdvnhg dw wkh vdph forfn f\foh lq wkh fdvh ri d :ulwh rshudwlrq 7kh wlplqj uhodwlrqv ehwzhhq wkh &.( wlplqj dqg '40 duh ghvfulehg lq )ljxuh d dqg e tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 41/49 figure 15. auto precharge timing (read cycle) (1) cas latency = 2 (a) burst length = 1 command read dq ap act q0 012345678910111213 t rp (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq (2) cas latency = 3 (a) burst length = 1 command dq (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq read ap act q0 read ap act q0 read q0 read ap act q0 t rp read ap act q0 t rp read ap act q0 t rp read ap act t rp q0 q1 q1 q2 q3 ap act q1 q2 q3 q4 q5 q6 q7 q1 q1 q2 q3 q1 q2 q3 q4 q5 q6 q7 note) ? represents the read with auto precharge command. ? represents the start of internal precharging. ? represents the bank activate command. ? when the auto precharge command is asserted, the period from the bank activate command to the start of internal precharging must be at least t ras (min). read ap act t rp t rp t rp tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 42/49 figure 16. auto precharge timing (write cycle) (1) cas latency = 2 (a) burst length = 1 command write dq ap act d0 012345678910111213 t rp (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq (2) cas latency = 3 (a) burst length = 1 command dq (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq write ap act d0 write ap act d0 write d0 write ap act d0 t rp write ap act d0 t rp write ap act d0 t rp write ap act t rp d0 d1 d1 d2 d3 ap act d1 d2 d3 d4 d5 d6 d7 d1 d1 d2 d3 d1 d2 d3 d4 d5 d6 d7 t wr t wr t wr t wr t wr t wr t wr t wr note) ? represents the write with auto precharge command. ? represents the start of internal precharging. ? represents the bank activate command. ? when the auto precharge command is asserted, the period from the bank activate command to the start of internal precharging must be at least t ras (min). write ap act t rp t rp t rp tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 43/49 figure 17. timing chart for read-to-write cycle (1) cas latency = 2 (a) command read dq write d0 012345678910111213 d1 d2 d3 dqm in the case of burst length = 4 (b) command read dq write d0 d1 d2 d3 dqm (2) cas latency = 3 (a) command read dq write d0 d1 d2 d3 dqm (b) command read dq write d0 d1 d2 d3 dqm note) ? the output data must be masked by dqm to avoid i/o conflict. tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 44/49 figure 18. timing chart for write-to-read cycle (1) cas latency = 2 (a) command read dq write q0 012345678910111213 q1 q2 q3 dqm in the case of burst length = 4 (b) command read dq write d0 d1 dqm (2) cas latency = 3 (a) command read dq write dqm (b) command read dq write dqm d0 q0 q1 q2 q3 q0 q1 q2 q3 d0 d0 d1 q0 q1 q2 q3 tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 45/49 figure 19. timing chart for burst stop cycle (burst stop command) dq bst q0 012345678910111213 q1 q2 q3 (1) read cycle (a) cas latency = 2 command read dq bst (b) cas latency = 3 command bst dq write (2) write cycle command read q4 q0 q1 q2 q3 q4 d0 d1 d2 d3 d4 note) ? represents the burst stop command. bst tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 46/49 figure 20. timing chart for burst stop cycle (precharge command) dq prcg q0 0123456789101112 q1 q2 q3 (1) read cycle (a) cas latency = 2 command read dq prcg (b) cas latency = 3 command prcg write command read q4 q0 q1 q2 q3 q4 (2) write cycle (a) cas latency = 2 prcg dqm write command d1 d2 d3 d4 (b) cas latency = 3 dq d0 t wr note) ? represents the precharge command. prcg dq d0 d1 d2 d3 d4 dqm t wr in the case of burst length = 8 tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 47/49 figure 21 (a). cke/dqm input timing (write cycle) (1) 1234567 dq dqm cke external clk cycle no. internal clk d1 dqm mask cke mask d2 d3 d5 d6 (3) 1234567 dq dqm cke clk cycle no. d1 cke mask d2 d3 d5 d6 d4 (2) 1234567 dq dqm cke clk cycle no. d1 dqm mask cke mask d2 d3 d5 d6 external internal clk external internal clk tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 48/49 figure 21 (b). cke/dqm input timing (read cycle) (1) 1234567 dq dqm cke external clk cycle no. internal clk q1 q2 q3 q6 (3) 1234567 dq dqm cke clk cycle no. q1 q2 q4 q5 q6 (2) 1234567 dq dqm cke clk cycle no. q1 q2 q3 q6 q4 open open q4 open q3 external internal clk external internal clk tc59sm916/08/04aft/aftl-70,-75,-80 2001-05-29 49/49 package dimensions unit: mm |
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